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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
Figure 3. AND Array
In[0]
In[34]
In[35]
PT0
PT1
PT2
PT3
PT4
PT75
PT76
PT77
PT78
Cluster 0
Cluster 15
PT79
PT80 Shared PT Clock
PT81 Shared PT Initialization
PT82 Shared PTOE
Note:
Indicates programmable fuse.
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term
cluster is associated with a macrocell. The cluster size for the ispMACH 4000 family is 4+1 (total 5) product terms.
The software automatically considers the availability and distribution of product term clusters as it fits the functions
within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path, 20-PT Speed
Locking path and an up to 80-PT path. The availability of these three paths lets designers trade timing variability for
increased performance.
The enhanced Logic Allocator of the ispMACH 4000 family consists of the following blocks:
? Product Term Allocator
? Cluster Allocator
? Wide Steering Logic
Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.
Figure 4. Macrocell Slice
to
to
from from
n -1 n -2
n -1
n -4
Fast 5-PT
From
n -4
1-80
PTs
Path
Cluster
n
to
5-PT
from
from
To XOR (MC)
Individual Product
Term Allocator
n +1
n +2
Cluster
Allocator
n +1
To n +4
SuperWIDE?
Steering Logic
5
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